One prior art method for fabricating SOI wafers is known as Separation by Implantation of Oxygen (SIMOX). This method typically involves using high-energy ions to implant a large dose of oxygen ions beneath the surface of a bulk Si-containing wafer, which unfortunately produces damage, such as dislocation loops, in the wafer. To control the final SOI thickness, it is necessary to Chem/Mech Polish (CMP). In addition, to achieve a perfect reliable Buried Oxide (BOX) along with SOI thickness, the following conditions must be met: 1) a high oxygen dose is necessary with uniform constant concentration to achieve uniform BOX thickness, which causes more damage, such as bigger dislocation loops, a contamination of the wafer because oxygen implantation introduces carbon and heavy metals, and also higher cost; 2) a high annealing temperature for a lengthy time produces better quality BOX, but it requires longer tool use and thus higher cost of the annealing tool (Lower temperature annealing is not able to remove the implantation damage totally and forms non-uniform oxide thickness, and the wafer results in larger dislocation loops and leakage at later steps in the integrated process); and 3) the cost of the BOX is proportional to both the oxygen implantation energy and dose and longer high temperature annealing, but higher energy causes deeper damage and more scattering of oxygen so that the desired depth/thickness of BOX as well as SOI is harder to control and creates higher production costs.
Another prior art method involves a wafer delaminating technique along with implantation. A beamline-type implanter by SOItech or a plasma immersion implantation chamber by Silicon Genesis is used. In both the SIMOX and SOITech/Silicon Genesis approaches, the entire wafer is formed with buried oxide, which eliminates the advantages and flexibility of fabricating a patterned SOI wafer having both BOX and bulk devices on the same wafer and chip.
All known prior art methods do not have the capability to fabricate both SOI and bulk devices on the same starting wafer, but are limited to SOI devices on SOI wafers or bulk devices on bulk wafers.
Current high performance technologies, such as CMOS, include embedded strained regions of, for example, eSiGe in pFET (compressive strain/stress for hole mobility enhancements) and, for example, eSiC in nFET (tensile strain/stress for electron mobility enhancements), preferably by a low to high temperature epitaxy process, after first forming recesses in a substrate. These embedded strained regions, which are in the substrate on either side of the channel region, are generally aligned to the gate of the FET and are doped in the same manner as the regular source/drain regions of the FETs. The embedded strained regions in the recesses function mainly to create a respective stress/strain (compressive strain/stress for pFETS and tensile strain/stress for nFETs) in the channel to increase carrier mobilities. This technology is not only applicable for strained layers but is also applicable for non-strained layers by growing epitaxy silicon in the silicon recesses.